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HP Shows Off PA-8800 SMP-On-A-Chip CPU Plans

timothy posted more than 12 years ago | from the chips-within-chips dept.

Technology 176

Eric^2 writes: "At last week's MicroProcessor Forum, HP's David J. C. Johnson unveiled the details of HP's latest RISC processor destined to redefine performance in Server-Class processors. Following a relatively simple strategy, the PA-8800 processor combines two PA-8700 cores on a single chip to enable symmetric multiprocessing (SMP) on a single processor. Aside from bumping the core speed up to an initial 1 GHz, enhancements include the addition of combined 35 MB L1+L2 cache. The article contains the full text. AMD, please steal an idea..."

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176 comments

And Get Sued? (1, Offtopic)

tomblackwell (6196) | more than 12 years ago | (#2460774)

These companies tend to patent anything that will give them a competitive edge in the marketplace. "Stealing an idea" would probably get them into some legal hot water, just like stealing a TV, or your car.

My New 3-STroke Lawn Tool R0x0r5! (-1)

benevolent_spork (446160) | more than 12 years ago | (#2460796)

The new edger attachement on my 3-stroke Ryobi (john deere) is just fcukign fantastic! I mean jeses fucking raspberries! It is queit and powerful and even more even efficient that the older two stroke technology of my fathers day! I read that it causes less pollutione than electirc too, when you factor in all the powre plants that make the juice.

Re:And Get Sued? (0)

Anonymous Coward | more than 12 years ago | (#2460815)

I think he's saying this jokingly. It is very feasible that AMD could come up a similar idead or license the rights to build SMP chips from HP.

Re:And Get Sued? (2)

C0vardeAn0nim0 (232451) | more than 12 years ago | (#2460867)

Not likely. HP is Intel's partner in the development of Itanium, which is based on PA-RISC.

If AMD has a desire to cram two AMD-64 in one package they better come with their own solution or license IBM's one...

Re:And Get Sued? (-1)

Anomymous_Spork (447035) | more than 12 years ago | (#2460833)

Legitimate first posts are NOT allowed.

please read the rules on first posting.

it must either contain a link to goatse.cx [goatse.cx]

or, it must be used to widen the page:


    • WWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWW WW





OR, it must link back to a previous slashdot article, indicating that it is a REPEAT [slashdot.org]

Just for the record, the last applies here: this story is in fact a REPEAT [slashdot.org]

Re:And Get Sued? (-1)

Dead Fart Warrior (525970) | more than 12 years ago | (#2460993)




    • WWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWW WW
    • IcouldaGottenAwayIfItWerentForThoseDamnSporks!



Slashdot.org, putting the 2nd W in WWW (that's right, there WIDE!)

Re:And Get Sued? (-1)

LinuxIsForAssholes (527253) | more than 12 years ago | (#2460837)

This was FP? WTF? Guys quit crapflooding the other stories and keep legitimate comments about an article from getting FP!

And you, tomblackwell, are an @ss|-|073, hence, Linux (which sucks) is for you.

Re:And Get Sued? (2, Informative)

Mifflesticks (473216) | more than 12 years ago | (#2460845)

It wouldn't be stealing an idea. This idea has been around for a long time in academia. Maybe the poster forgot this, but the POWER4 from IBM does this, and comes with 32Mb of L3 cache, plus an ondie shared L2 cache. The idea isn't new, it's known as CMP (Chip-level Multi-Processing). Really, "SMP on a chip" is merely called CMP.

Also, though Sun has decided not to use the MAJC architecture for anything (they were hoping to try to get it to become a video-accelerator, but that's not even going to happen, most likely), that too was fully spec'ed out to have multiple cores on a chip...it's really nothign new :)

The longstanding rumour is that AMD will be coming out with a dual-hammer processor (ie, CMP). In academia, the idea has been used frequently as well.

The idea of using CMP isn't even that big a deal to most consumers. While it would be nice for AMD to come out with a chip that does multithreading (merely because it increases real-world throughput quite a bit, depending upon the type of multithreading), the average PC running windows 9x/ME/ XP Consumer won't be able to multithread anyway. The only reason for AMD to multithread is for the server-space, which is what they're aiming for with the hammer series...but I digress.

Re:And Get Sued? (0)

Anonymous Coward | more than 12 years ago | (#2460879)

Heck, I still have a paper from a C.S. class (1992) where I was suggesting the idea of combining cores on one chip to enable faster SMP. Would that be prior art? Funny thing is, the prof said it as a stupid idea.
Hey Dale Grit, are you listening?

Re:And Get Sued? (0)

Anonymous Coward | more than 12 years ago | (#2461075)

He said "idea", not end result. It's not illegal to use someone else's idea as long as you don't build the same product using his method (which is likely patented).

Did Gore Win?: From The Daily Telegraph in U.K. (-1, Offtopic)

Anonymous Coward | more than 12 years ago | (#2461160)

from The Daily Telegraph [slashdot.org]

You have to go the site and search on "Gore":

Did Al Gore win after all? US newspapers
would rather not say
By Charles Laurence in New York
(Filed: 21/10/2001)

Did Al Gore win after all? US newspapers
would rather not say
By Charles Laurence in New York
(Filed: 21/10/2001)

THE most detailed analysis yet of the contested Florida
votes from last year's presidential election - with the
potential to question President Bush's legitimacy - is being
withheld by the news organisations that commissioned it.
Results of the inspection of more than 170,000 votes
rejected as unreadable in the "hanging chad" chaos of last
November's vote count were ready at the end of August.
The study was commissioned early this year by a
consortium including the Wall Street Journal, the
Washington Post and the New York Times, the nation's
most powerful newspapers, and the broadcaster CNN.
It was regarded as a means of supplying final answers to
the nagging questions over President Bush's razor-thin
victory margin. The cost was more than ú700,000.
Now, however, spokesmen for the consortium say that
they decided to "postpone" the story of the analysis by
the National Opinion Research Centre (NORC) at the
University of Chicago for lack of resources and lack of
interest in the face of the enormous story of the
September 11 attacks and the subsequent "war on
terrorism".
Newspapers were saying last week that the final phase of
the analysis, the actual counting of the 170,000 votes,
had been "postponed" but would become known at an
appropriate time.
America's liberal newspaper establishment originally set
up the commission in the belief that it would discover that
Al Gore was the winner of the Florida count.
Their hope for a Gore victory appears to have been
sacrificed on the altar of patriotism and a perception that
America needs to be led into war by a strong president.
"Our belief is that the priorities of the country have
changed, and our priorities have changed," said Steven
Goldstein, the vice-president of corporate communications
at Dow Jones and Co, the owners of the Wall Street
Journal.
Catherine Mathis, a spokesman for the New York Times,
said: "The consortium agreed that because of the war,
because of our lack of resources, we were postponing the
vote-count investigation. But this is not final. The intention
is to go forward."
However David Podvin, an investigative journalist who
runs an independent web page, Make Them Accountable,
said he had been tipped off that the consortium was
covering up the results.
He refused to disclose his source other than to describe
him as a former media executive whom he knew "as an
accurate conduit of information" and who claimed that the
consortium "is deliberately hiding the results of its recount
because Gore was the indisputable winner".
He also claims that a New York Times journalist who was
involved in the recount project had told "a former
companion" that the Gore victory margin was big enough
to create "major trouble for the Bush presidency if this
ever gets out".

second toast?????? (-1, Offtopic)

Anonymous Coward | more than 12 years ago | (#2460777)

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It's been 13 seconds since you hit 'reply'!

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Hmmm Sounds Like IBM (2)

devinoni (13244) | more than 12 years ago | (#2460780)

The IBM p690 server uses POWER4 processors. Each
chip has 2 POWER cores with high-speed interconnects. Even better is that each chip is connected to 3 other chips to make up 8 CPU packs.

Now if i could only get that i my pda (0)

Anonymous Coward | more than 12 years ago | (#2460788)

then i'd be happy.

Trolls and Slashbots (-1)

The Turd Report (527733) | more than 12 years ago | (#2460793)

Trolls and Slashbots: A Symbiotic Relationship

If you ask the average slashbot, he (I can say he with confidance, cause no women use linux) would tell you that he would want the troll off of slashdot as soon as possible. I argue that slashdot needs trolls to be what it is today. Most posters to slashdot are repressed geeks that no one cares about and everybody pickes on. They are never on the winning team and are always left out. Slashdot readers have latched on to Linux and the community that has arose around it; they love to defend it; even if they are wrong.
Most trolls are helpful and caring folk who care about their fellow man. Trolls help the poor linux user by giving him a easy target to flame, or to attempt to flame, as the case me be. Troll try to be there for slashdot readers of a wide variety of mental capacities. Some trolls are easy to spot; they are designed to be that way. But, to give some of the smarter (and that term is very subjective) slashdot readers a challenge, some of the trolls are harder to spot. The troll might be an easy topic, like the death of BSD, or it might be a harder topic like Natilie Portman and the grits that occupy her pants.
No matter what the level of trolling, it can be said hat slashdot readers love responding to trolls as much as much as the trolls like being responded to. Keep in mind that when a (logged in) troll makes a first post or gives a link to goatse.cx, it is his way of saying "I love you, man!"

Please discuss

Re:Assertion Failed:Yuo!=ToothlessCumDrenchedWhore (-1)

benevolent_spork (446160) | more than 12 years ago | (#2460861)

Ha ha

In other news:

Anonymous Coward Dies at IQ 58

Anonymous coward died messily today in a pool of its own feces at the tender IQ of 58. Sources close to the fag say that he died in a gay penis festival gone horribly awry. Timothy Henchfaglet, another close asshumping homosexual friend of the AC, said he died while jumping from a 3 foot step ladder onto a 48 inch didlo held erect by the cum guzzling queer-extroardinaire, michael the censor.

Re:asshole (-1, Offtopic)

Anonymous Coward | more than 12 years ago | (#2461032)

Benevolent_spork is an asshole

Re:Trolls and Slashbots (-1)

Dead Fart Warrior (525970) | more than 12 years ago | (#2461045)

*sniff*

I think I have something in my eye.... I'll be in the bathroom...

Re:Trolls and Slashbots (-1)

The Turd Report (527733) | more than 12 years ago | (#2461144)

Thanks for your support

How much cache??? (2)

larien (5608) | more than 12 years ago | (#2460797)

Wow... And I thought the 8MB L2 cache on UltraSPARC IIIs was a lot, not to mention the 16MB on some IBMs. Now we're talking about 3MB just in L1 with 32MB L2 cache. This beasty should have some impressive benchmark scores (yeah, I know, benchmarks aren't everything...)

Re:How much cache??? (0)

yobbo (324595) | more than 12 years ago | (#2460965)

What is faster - a large high latency level 1 cache, or a small but low latency level 1? Intel bet on the latter with pentium 4, having an extremely small level 1 but making up alot of performance due to the fact that it was single latency, as opposed to the Athlon which is either 2 or 3 cycle (?) Sun seems to think more along the lines of AMD. Have a large level 1, and hope that the sheer amount of stuff that fits in your level 1 makes up for the performance you lose due to the fact that it takes longer to actually access the data. Only in this case, Sun is going with a..... absolutely *huge* L1... interesting

It'll be very interesting to see how future processor designs go, if we do in fact see designs branch in different directions. Then again, it may appear awkward that i'm comparing x86 designs to SPARC, but seeing AMD will be hoping to compete head on using x86-64, i think it will be relevant. Especially considering the initial spec number published for Sledgehammer. 1400 in specint, WOAH!

Re:How much cache??? (1)

LenE (29922) | more than 12 years ago | (#2461119)

The latency issue just isn't an issue with the SPARC, or any other modern RISC-ish architectures. Out of order execution and branch prediction techniques can accomodate latencies. Cache size though, is much more important, as a larger cache can hold many queued instructions and data, which will be fed in a constant stream to the processor without having to revert to slower memory.

In the P4, 20 stage pipeline and it's prediction logic are much more succeptible to cache latency problems. Waiting two or three cycles for data on a P4 could cause major pipeline hiccups.

-- Len

Re:How much cache??? (1)

CBravo (35450) | more than 12 years ago | (#2461263)

don't lie. Latency problems are totally program dependant. You can't cache new data ...

The L2 cache of the P4 probably has a # cycles latency, but I don't think it is a problem. In fact it could be a reason to implement extreme pipelining (so you can make 'small' steps towards computing the result instead of only being able to take big steps). Waiting for main memory _is_ a problem, _BIG_ problem.

I really wonder where you get your ideas.

What about? (-1, Redundant)

Anonymous Coward | more than 12 years ago | (#2460808)

A Beowulf cluster of these babies!
Didn't HP dump the PA-RISC line for the Intel/HP joint venture?

Re:What about? (0)

Anonymous Coward | more than 12 years ago | (#2460838)

Wow, modded down in less than 0.3 seconds! Light speed moderation, I have a patent, and you owe me.

Re:What about? (-1)

The Intrepid Travell (528524) | more than 12 years ago | (#2460871)

Yeah. I think that [www.modera...suck.balls] .

duplication of effort (0)

Anonymous Coward | more than 12 years ago | (#2460814)

wow, that sounds a lot like IBM's release re: the Power4... except not as interesting

just to make sure nobody is misled... (4, Interesting)

turbine216 (458014) | more than 12 years ago | (#2460817)

...a 1 GHZ processor may not sound like much, even in this dual-core configuration, but keep in mind that this is a RISC processor. None of that Super-mega-ultra-long-50-bazillion-stage pipeline crap that Intel uses to pump up their MHz rating. The article kind of sells this point a little bit short. The RISC architecture allows this processor to do roughly twice as much work in the same amount of time - or, to put it in a more concrete scenario: imagine a pair of 2GHz Pentium 4's running in SMP configuration.

Now that's FAST .

3 questions... (-1, Offtopic)

Anonymous Coward | more than 12 years ago | (#2460860)

Do you work for apple? Are you 13? And if yes to the second question, are you female and nubile?

U R A Fag (-1)

LinuxIsForAssholes (527253) | more than 12 years ago | (#2460910)

'nuff said

Re:just to make sure nobody is misled... (1)

Ozric (30691) | more than 12 years ago | (#2460921)

It is not just the cpu, Think about the I/O in the HP9000. Now that's FAST

Why is this at +3? (-1, Offtopic)

Anonymous Coward | more than 12 years ago | (#2460951)

He's not even smart enough to be a truly funny troll, do the people who vote for this have so little sophistication that they consider this well disguised sarcasm?

Re:just to make sure nobody is misled... (0)

Anonymous Coward | more than 12 years ago | (#2461055)

Now now... you and I both know that's a bit of bull. You really can't compare Mhz between a RISC and a CISC, simply because the CISC processor likely has instructions which, translated to a RISC architecture, would require 2 or 3 instructions. The result, RISC programs are much larger, and the processor has to execute many more instructions to perform the same task as a CISC. OTOH, on the RISC, there is more opportunity for pipelining and other optimizations, but the point is, comparing a RISC to a CISC based purely on Mhz is really like comparing Oranges to Lemons. They're similar, but really not the same.

Re:just to make sure nobody is misled... (0)

Anonymous Coward | more than 12 years ago | (#2461072)

Gawd, talk about a troll-o-rama. Yeah, and the Macintosh is "twice as fast" as the equivalent Intel processor.

Sorry bud, but RISC is not some magic incantation.

Re:just to make sure nobody is misled... (1)

warpSpeed (67927) | more than 12 years ago | (#2461089)


It might be fast, but imagine the heat sink on that puppy. It could heat my pool... in the middle of winter.

~Sean

Re:just to make sure nobody is misled... (5, Informative)

svirre (39068) | more than 12 years ago | (#2461102)

Risc or cisc architecture primarily affect the complexity of the fetch and decode stages of the CPU.

The famous Intel-pipeline is in the execute stage (ALU).

Pipelining is a strategy which is equally valid for both risc as in cisc architectures, and a risc architecture do not offer any complexity advantage in the execute stage. After all a multiplier is a multiplier regardless of overlaying architecture.

Nowdays we don't really see much diffrence in performance between risc and cisc architecures for upscale processors. This is because the savings in fetch and decode logic are dwarfed by other costs like prefetch, reordering and brach prediction (which are used for both architectures).

My hairy asshole is 2 inches in diameter (-1, Flamebait)

Anonymous Coward | more than 12 years ago | (#2461169)

Man oh man. Natalie portman was on that concert for NY on VH1 with some firefighter introducing Elton John. She probably ran backstage and sucked that guy off in the dressing room as soon as that faggot Sir Elton took the stage. Doesn't that just burn you? Hehe get it?

Now, before you start flaming little old me, remember that it's not me you're pissed off at, you're just "projecting". You're really pissed out at those greedy pussy hoarders at the NY fire department like Steve Buscemi. Fuckin' Bastards!

An old idea.... (0, Troll)

gatkinso (15975) | more than 12 years ago | (#2460819)

Intel jammed two 486 cores on a chip and called it a "Pentium."

Gross simplification is a viable debating tactic, BTW.

Re:An old idea.... (-1)

DivineOb (256115) | more than 12 years ago | (#2460880)

You're just plain wrong...

so, either you're intentionally being dumb or are totally clueless... take your pick...

Re:An old idea.... (0)

Anonymous Coward | more than 12 years ago | (#2460942)

Or, hee's trolling for idiots... WOAH! Looks like he caught another one!

Re:An old idea.... (-1)

DivineOb (256115) | more than 12 years ago | (#2461074)

damn :/... looks like I suck :(

Practical Ideas (0)

Renraku (518261) | more than 12 years ago | (#2460822)

It doesn't seem too practical to me. Most apps don't benefit greatly from SMP anyway. Add to that the potential heat problems caused by two cores on one chip...Why not just go with a more traditional SMP approach? At least you won't have to worry too much about heat then.

Re:Practical Ideas (0)

Anonymous Coward | more than 12 years ago | (#2460859)

These type of processors are designed for servers. The machines often have at least 8 or all the way up to 256 processors in them. Doing this allows the processors to communicate with each other at a higher speed.

These type of machines run in air conditioned enviroments and have jet engines for cooling fans.

Re:Practical Ideas (0, Troll)

psavo (162634) | more than 12 years ago | (#2460902)

It doesn't seem too practical to me. Most apps don't benefit greatly from SMP anyway. Add to that the potential heat problems caused by two cores on one chip...Why not just go with a more traditional SMP approach? At least you won't have to worry too much about heat then.

Yo! Helloou? Where are you living man? In what decade? This is year 2001 and most of "cooperative multitasking" crap is buried in hell with windows 3.1 and alikes. Even MacOS is phasing out (though that one worked out pretty nicely [because of interface built that way])
You get tremendous boost when using SMP. There's no way to describe it, it's just awesome!

Remember, you run pretty many tasks continuously, and simultaneously! There's maybe apache, mozilla, bluefish, emacs & others running all the time! For chrissakes, why do you think distros make X 'nice -10'? Most of the applications are multithreaded by now, not doing it is just insane, simply because of different overheads & application responsiviness.

Just think for a moment before posting something like that..

Its compatible with Itanium moterboards (2)

DABANSHEE (154661) | more than 12 years ago | (#2460991)

That seems practicle enough to me.

You know when AMD 1st brought out the Athlon they were spose to be compatible with Alpha 21264 boards too.

AMD even made a couple of engineering samples in slot B packages for testing but that's as far as it it.

If someone could hack a slot A/Slot B adaptor then they could hypothetically do the same thing. They might have to hack a bios update to though.

Re:Practical Ideas (4, Informative)

NerveGas (168686) | more than 12 years ago | (#2461150)

It doesn't seem too practical to me. Most apps don't benefit greatly from SMP anyway.

They don't? What kind of server do you run? Most all pieces of production-class server software that I know of benefit from multiple processes. Look at Apache, forking off five, ten, or even more processes to handle requests. MySQL, I believe, uses threads. PostgreSQL forks off a new backend for each connection. Shoot, even your telnet, ftp, ssh, and mail daemons will fork off for each connection, allowing you to take advantage of more than one CPU.

If you're sitting at home working on a spreadsheet, you're right, SMP isn't for you - and this machine isn't targetted at you. When you're running a server that may have tens, hundreds, or thousands of SIMULTANEOUS processes fighting for CPU time, every processor counts.

And, to make things even better, even if you're only running a single, non-threaded process, having two processors still makes the machine much more "responsive", as the second CPU can handle kernel code for file IO, network code, interrupt handling, writing to logs, and a lot of other tasks. Ever seen how much CPU time even syslog can chew up?

steve

Did I read that right? (4, Insightful)

ruiner13 (527499) | more than 12 years ago | (#2460824)

Did that say 35MB of L1 + L2 cache? I may be rusty, but I think I remember reading in my Processor Design for Dummies book that increasing cache size actually can slow down processor performance after a certain amount. Could someone please clarify this?

Re:Did I read that right? (1)

Mifflesticks (473216) | more than 12 years ago | (#2460866)

It can hurt performance because the larger the cache, the higher it's latency is going to be. Of course, the larger it is, the higher the hit-rate in that cache, so it's less likely to have to go down another level in the memory hierarchy.

Using more caches of varying sizes is actually better than a monolithic cache, for reasons you described. If there are more caches, the primary one can focus upon low-latency, the second for high-bandwidth, and the third for high-hit-rate.

But yes, it is indeed 35Mb of caches, though it's worthy of note that the L2 cache is off-die.

Re:Did I read that right? (1)

NerveGas (168686) | more than 12 years ago | (#2461122)

As the CPU frequencies outstrip memory frequencies by larger and larger margins, the cost of a cache-miss increases - and so does the number of cycles a chip can afford to use looking through the cache. Because of that, the amount of cache where it stops making sense to add more is much, much higher than it was five years ago.

Intel chips, though, keep using about the same overall amount of cache, to keep costs down.

steve

Re:Did I read that right? (2)

bmajik (96670) | more than 12 years ago | (#2461170)

the ratios between memory heirarchies should be taken into consideration when designing any layer. For instance, increasing vastly the size of the L2 cache will make the L2 hit ratio go up, but the L1 hit ratio go down (assuming the inclusion policy is in effect - this is not always so anymore -- see the 1st generatino Duron chips)

Similarly, adding more ram to a machine _could_ slow it down in some situations because the "overall" cache hit ratio could go down.

Also, when caches get to be too large, the cache policy may need to be changed. A fully associative cache is the most flexible placement policy and can give great hit ratio for a large working set, however, a fully associaive cache search takes longer than a direct map "search" or a set-associative search.

So, if to get a large cache size they had to go to set assoc or direct mapped, then that will generally lower the hit ratio vs a cache of the same size which is fully assocaitive.

It's all tradeoffs basically. You could write a cache simulator to play around with this :)

Don Rumsfeld licked Anthrax spores from my asshole (-1, Offtopic)

Anonymous Coward | more than 12 years ago | (#2461221)

Yes, that's right. Secretary of Defense Rumsfeld helped me out by licking some of those pesky Anthrax spores out of my rectum so I didn't get any cutaneous hemhorroids.

Then afterwords we sat around and watched TV, he was really pissed off that someone leaked to the press about the ground invasion over the weekend. Then he licked my asshole again just to make sure.

AC RULEZ!!!!!

Re:Did I read that right? (2)

be-fan (61476) | more than 12 years ago | (#2461223)

Yea, I gagged a little myself the first time I read it. Until I remembered that HP was the one who put 1.5 MB caches on chips in the PII era.

Right... DON'T CARE (-1, Troll)

The Intrepid Travell (528524) | more than 12 years ago | (#2460828)

This is true, and it sucks. I really don't care what you mods have to say to me. That's right... give it to me low. Knock me down! See if I won't just get back up again.

Cocksmokers

Smokin (1, Informative)

thetechweenie (60363) | more than 12 years ago | (#2460832)

Why hasn't someone else done something like this? I would pay whatever it cost to get even an 8MB L1 & L2 Cache. Anyone want to make me one?

Re:Smokin (0)

Anonymous Coward | more than 12 years ago | (#2460878)

Because it's expensive, the yields are low, and in bigger processes (> 0.2um), the chips would have been huge.

Re:Smokin (0)

Anonymous Coward | more than 12 years ago | (#2460911)

Sun's been selling them for a while now. Go check out the Blade 1000, dual 900MHZ CPUS each with 8MB L2...

Re:Smokin (1)

thetechweenie (60363) | more than 12 years ago | (#2461033)

Do any /. readers have one of these? I'ld love to see a benchmark of one of these, and a similair sparc or something. Maybe TomsHardware could pull something like this off? Anyway, the price would be worth the geek factor.

Re:Smokin (2, Informative)

T-Punkt (90023) | more than 12 years ago | (#2461124)

"whatever it cost"?

Then go an buy something from Sun, IBM, Compaq -> AFAIK all three buy servers with that large L2 Caches. (Maybe HP and SGI as well).

E.g. something from IBM's z900 serie (mainframe - up to 32 MB L2 (per CPU?)) or pSeries 620 (workgroup/midrange server - up to 8MB L2 per CPU) or Sun Enterprise 450 (workgroup server - up to 8MB L2 Cache per CPU), Sun Fire 15K (High End Server, 8MB L2 per CPU), Compaq Alphaservers GS/ES series (up to 8MB per CPU).

And if you want just total of 8MB a SGI Origin 300 with more than 4 CPU should do it as well (2MB L2 per CPU).

WOW!!! (0)

Anonymous Coward | more than 12 years ago | (#2460849)

Just imagine a Beowulf cluBLAM!!! Thud.

Re:WOW!!! (0)

Anonymous Coward | more than 12 years ago | (#2461058)

cooled with hot grBLAM!!!... uh, smells like nataBLAM BLAM!!! Thud. goaSTOMP!! urghh...

Can you please clarify? (-1, Troll)

The Intrepid Travell (528524) | more than 12 years ago | (#2460853)

What does this have to do with goat sex? Seriously... what has slashdot become... FIRST POST, BITCHES!

Siroyan's OneDSP (2, Informative)

Anonymous Coward | more than 12 years ago | (#2460858)

The most interesting parallel architecture I heard about at the MPF was Siroyan's [siroyan.com] OneDSP architecture. This is a clustered VLIW machine that can execute up to 64 instructions each cycle! See the EE times article [eet.com] and their MPF paper [siroyan.com]

Re:Siroyan's OneDSP (1)

Mifflesticks (473216) | more than 12 years ago | (#2460886)

I bet the compiler guys are gonna have fun statically scheduling 64 instructions each cycle! (if you can't tell, I'm dripping with sarcasm, as Intel is even having a tough time scheduling 6 per cycle...though this is a DSP, so that makes it's application much better).

Of course... (0)

Anonymous Coward | more than 12 years ago | (#2460890)

It has the clock frequency of a 300bps modem's dsp. That's still pretty darn cool! *shrug*

Re:Of course... (0)

Anonymous Coward | more than 12 years ago | (#2461063)

It should be noted that this is a synthesizable processor core (like ARMs) and so 200MHz is pretty respectable. (The fastest synthesisable core is about 360MHz and issues 1 instruction per cycle).

Thanks, Rob! (0)

Anonymous Coward | more than 12 years ago | (#2460874)

" One guy wrote that we should take all these Legos and build giant robots with which to attack Afghanastan. [npr.org] " -- Rob Malda, Founder of Slashdot, a "News for Nerds" website, in a NPR report on post WTC gen-X, 10/22/2001

I, for one, would like to take a moment to thank Rob for setting us "Nerds" back where we belong. Way to make us look like a bunch of childish tech-heads with no conception of the real world! As a troll, I think it's high time that you slashdotters got slapped down for the idiotic geeks that you are! (That was sarcasm, you nincompoop!)

Two CPUs on a chip. (5, Informative)

Animats (122034) | more than 12 years ago | (#2460904)

That makes sense. Two CPUs on a chip isn't a new idea, though. The IBM Power4 [zdnet.com] PowerPC chip is very similar, with two PowerPC processors on the same die. There's even a module with 4 such chips [google.com] (8 processors) inside a machined aluminum block. That's intended as a building block for supercomputers.

Earlier steps in the multi-CPU direction included the 8-way DEC Alpha (killed in the merger with HP?) and a little National Semiconductor product for embedded systems with two very modest CPUs on a chip.

Re:Two CPUs on a chip. (1)

questionlp (58365) | more than 12 years ago | (#2461127)

Earlier steps in the multi-CPU direction included the 8-way DEC Alpha (killed in the merger with HP?) and a little National Semiconductor product for embedded systems with two very modest CPUs on a chip.
The IP for Alpha is now in the hands of Intel rather than Compaq (or Hewlett Paqard). I'm not sure if Intel will assimilate the technology into their IA-64 processors, release it as a high-end EV7 processor, or just kill it altogether.

Chuck Moore (1)

LazyDawg (519783) | more than 12 years ago | (#2460912)

Doesn't Chuck Moore's 25x already do SMP-like things, at a few billion instructions per second? Last time I checked he was using a 20-word instruction set on a stack-based computer, which IMO counts as RISC.

This is hardly new, but HP's version probably uses some fancy new lithography, and wins when it comes to clock speed.

Its MISC and its slow (0)

Anonymous Coward | more than 12 years ago | (#2460982)

With no such niceties as virtual memory, large address spaces, fast additions etc etc there is not a lot of software which would run well on them.

1GHz, that is sooooo slow (0, Troll)

Red Moose (31712) | more than 12 years ago | (#2460919)

1GHz? Man my Pentium 4 2GHz beats all these supposedly "fast" chips. It's HALF the speed, for christ's sake. That is sooooooooo quarter 3 2000.

2GHz, that is sooooo slow (0)

Anonymous Coward | more than 12 years ago | (#2461029)

You asked for it; here's some yummy troll food fer ya:

For the last time, clock speed doesn't compare between architectures. This is a RISC processor with a short pipeline, the pentium 4 you drool about (but don't really have) is a CISC with an extra-long needlessly-clock-boosting pipeline. Of course, you'd know this if you read the article.

If you read the specs, you'd see: "Speaking of performance, each PA-8700 RISC core delivers a SPEC performance of around 550 (for both Int and FP) at 750 MHz and the dual core PA-8800 running at 1 GHz will start out at a minimum of 900 / 1000 SPEC2000 int/fp scores, according to very conservative estimates."
A 2GHz P4 is in the 650 SPECINT/670 SPEC2000FP range, so basically each PA processor is about 10% faster.

Was it trolliscious? satisfied? oh, furry troll, why do I even bother feeding you?

Re:1GHz, that is sooooo slow (0)

Anonymous Coward | more than 12 years ago | (#2461047)

shut up

HP PA-8800 integer numbers (3, Offtopic)

Spootnik (518145) | more than 12 years ago | (#2460930)

PA-8800 lets you create two opposite predicates in one instruction, for example the predicate a<b and a>=b.

This seems to indicate that there are no separate "do this if predicate is true" and "do this if predicate is false" instructions, so for opposite predication you would have to specify two different predicates.

The processor cannot know that these two predicates are related, so this would give you quite a problem.

As has been publicly disclosed, in general in PA-8800, an instruction reading any resource (such as a predicate) must be in a later instruction group (cycle) than the instruction writing that resource. As a special case, branches are allowed to use a predicate written by another instruction in the same instruction group (as shown in the IDF slides).

So, the straightforward (but slow) PA-8800 schedule for the earlier example:

if (a < 0)
b += a;
else
b -= a;
c += b;
d += b;


would be:

cmp.lt pLT, pNLT = a, 0 // pLT & pNLT are 2 complementary preds
;;
(pLT) add b = b, a // add to b [then]
(pNLT) sub b = b, a // or sub from b [else]
;;
add c = c, b // uses of b
add d = d, b
;;


which takes 5 instructions in 3 cycles. (Note: In PA-8800 assembly, ";;" indicates the end of an instruction group, "=" separates the target operand(s) from the source(s), "//" begins a comment, and (pred) specifies the controlling predicate.)

An alternate (faster) schedule in PA-8800 is as follows:

sub bTmp = b, a // speculatively sub from b (into temp)
add b = b, a // and add to b
cmp.lt pLT, pNLT = a, 0
;;
(pLT) add c = c, b // uses of b [then]
(pLT) add d = d, b
(pNLT) add c = c, bTmp // uses of b (temp) [else]
(pNLT) add d = d, bTmp
(pNLT) mov b = bTmp // move bTmp to b [else]
;;


This takes 8 instructions in 2 cycles and one extra register. The final move of bTmp to b can be eliminated if b isn't live out at that point.

Re:HP PA-8800 integer numbers (-1)

Dead Fart Warrior (525970) | more than 12 years ago | (#2461023)

Can you translate into Visual Basic for me?

Just imagine (-1)

LinuxIsForAssholes (527253) | more than 12 years ago | (#2460934)

a beowulf cluster of these!!!

Er... (2, Interesting)

Glock27 (446276) | more than 12 years ago | (#2460946)

A couple of points:

Following a relatively simple strategy, the PA-8800 processor combines two PA-8700 cores on a single chip to enable symmetric multiprocessing (SMP) on a single processor.

It doesn't enable SMP "on a single processor". It provides two processors on a single die. There is a distinction.

AMD, please steal an idea...

The big rumor regarding the third version of Hammer is that it'll be a dual-CPU module. Any guesses as to Hammer's clock speed on release?

299,792,458 m/s...not just a good idea, its the law!

The BIG difference between PA8800 and Power4 (3)

zensonic (82242) | more than 12 years ago | (#2460952)

...is that you actually can go out and buy a new mainframe using Power4. Nothing wrong with looking ahead, but if you remember, AMD said that the Athlon should have been made in an "Athlon Ultra" version spotting 8MB L2 cache. .... I still stick to the motto: "I'll belive it when I can buy it"

JonKatz licks dirty @$$h0le$ (-1)

LinuxIsForAssholes (527253) | more than 12 years ago | (#2460954)

Slow Down Cowboy!
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Wait a minute! (0)

UltraBot2K1 (320256) | more than 12 years ago | (#2460957)

This is getting rediculous. Symmetric Multiprocessing on a single chip? That's impossible, unless you're just screwing around with semantics. I mean, think about it. You need TWO chips, at least, in order to engage in SMP, and anyone who says otherwise is putting out meaningless hype. SMP on one chip, or just vaporware?

Re:Wait a minute! (1)

NerveGas (168686) | more than 12 years ago | (#2461077)

If you had taken even thirty seconds to read the blurb, you would see that they have indeed put two cores on one chip, which gives you two processors on a chip. Remember, "processor" != "chip".

It's the same idea as Via combining the north and south bridges on some of their motherboard chipsets. They take the two cores, and put them on a single wafer, with a bus (still on the same wafer) between them.

The idea really isn't revolutionary. Ever since microprosessors were invented, the trend has been to pack more and more onto a single chip, as it reduces cost, complexity, and design complexity while increasing compatibility and (most importantly) bandwidth. While your fastest P4 front-side bus chugs along at 400 MHz, busses that are kept on the wafer can run at full core frequency, even in the gigahertz range. Plus, you can run a lot more of them, and since the distances covered are shorter, it's easier to avoid external RF interference. And in multi-processing computers, the connectivity between cores is vitally important.

Look at a lot of motherboard chipsets these days. In one or two chips, they'll have circuitry for video, audio, modem, network, IDE, floppy, serial, USB, PCI, and memory controllers, to name just a few. One of the long-term goals that some companies have been talking about is "SOC", or "System On A Chip", where a single chip will have everything you need for a computer. At the point where the CPU has all of the other controllers inside of it, not only could performance increase dramatically, you could potentially use a motherboard for any CPU that you wanted, as all the motherboard would do is provide power to the CPU and traces from the CPU to the connectors for external componants.

steve

Re:Wait a minute! (0)

Anonymous Coward | more than 12 years ago | (#2461091)

two cores on one chip. not that hard to do.

idiot.

Re:Wait a minute! (1)

polarkittycat (454695) | more than 12 years ago | (#2461094)

Think of it as two cores....

*cough*IBM*cough* (0)

Anonymous Coward | more than 12 years ago | (#2460960)

IBM unveiled its SMP-on-a-chip solution, the Power4, almost 2 weeks ago. 64 bit PowerPC. And only 2 OS'es run it.

One of them is Linux.

Re:*cough*IBM*cough* (-1)

LinuxIsForAssholes (527253) | more than 12 years ago | (#2460990)

yeah, but Linux sucks turds, so what's your point?

IBM is for assholes too

Re:*cough*IBM*cough* (0)

Anonymous Coward | more than 12 years ago | (#2461028)

64 bit PowerPC. And only 2 OS'es run it. One of them is Linux.
This is why I love Linux. When you have a new chip, all the chip makers know that Linux should be the first OS to run on it. For example, Linux was the first OS to run on AMD's 64 bit chip, and Linux was the first OS to run on Intel's Itanium 64 bit chip, the flagship of the Intel line . Linux is changing the way we think about computing.

Re:*cough*IBM*cough* (-1)

LinuxIsForAssholes (527253) | more than 12 years ago | (#2461064)

Linux is changing the way we think about computing.

Changing the way who thinks about computing. And what does it make them think about? Going to a paper office because paper fileing is in the long run less expensive and more efficient than Linux?

Re:*cough*IBM*cough* (0)

Anonymous Coward | more than 12 years ago | (#2461156)

Paper filing can be good. There used to be a special type of filing cards that had holes and notches that could be punched out and you could sort the cards in various ways by inserting steel rods into the cards. Different notches would correspond to different characteristics assigned to the information on the card. Simple, and easier to learn than MySQL.

How much will one of these cost? (0)

Anonymous Coward | more than 12 years ago | (#2460998)

compared to say a 2.2GHz P4 or an Athlon XP 1800+. Inquiring minds want to know.

Re:How much will one of these cost? (-1)

LinuxIsForAssholes (527253) | more than 12 years ago | (#2461002)

More than your pathetic, pissant, paynothing job pays your worthless a$$

Here is a link to an IBM white paper (0)

Anonymous Coward | more than 12 years ago | (#2461016)

http://www-1.ibm.com/servers/eserver/pseries/hardw are/whitepapers/p690_config.html#arch

What about Itanium? (2)

Grishnakh (216268) | more than 12 years ago | (#2461053)

I thought HP had committed itself to ditching the PA-RISC and moving to Itanic, err, Itanium.

When do you think they will have Transparent SMP? (0)

AnonymousCowheard (239159) | more than 12 years ago | (#2461066)

Who says the OS needs to know there are two or 4 or 6 CPUs in a system? Threaded programming works best only on Clusters. SMP scales poorly on Intel Pentium IV's because maybe that isn't a reason to use two Pentium IV CPUs...Each CPU provides more resource management. Someone should've written some supporting text on "the SMP myth" which includes why SMP is not a good and efficient solution to increase calculation performance on a given workstation. Pentium Pro CPUs provide BUS Mastering in SMP mode and the secondary CPU provides upto %30 of extra system performance. Of Course, for every extra CPU in a Pentium Pro system, it adds 30% - (NumCPUs*5) performance due to scheduling in the software. It is always the Primary CPU in a multi-cpu system that must schedule events for the Secondary, Tertiary, and Quaternary cpu in software. On a Pentium Pro CPU, that requires somewhere around 10% of that Primary CPU's processing power to schedule software for that second CPU; it's around 15%/20% for the 3rd, etc. That's why you see Dual Pentium IV Workstations not performing upto par with another workstation with only one Pentium IV. It's SMP doesn't scale well. The only value of multiple-CPUs is for BUS Mastering and providing more system resource management. Intel abandoned BUS Mastering in SMP systems after the Pentium Pro. So, for the extra cost of using a second Pentium IV CPU, it isn't worth it. Just get a nice Pentium Pro Server [ebay.com] on eBay and you will get your money's worth for those extra CPUs; which provide BUS Mastering. Pentium Pro has always been a nice CPU. You can scramble an egg in 5 minutes, versus 15 for the Pentium IV.

How does it compare to the MAJC spec? (1)

zor_prime (42665) | more than 12 years ago | (#2461107)

Reading through the article, this design seems to share a lot in common with Sun's MAJC architecture. Both allow for multiple cores on a single chip. Anyone else notice the similarities?

I guess the biggest difference would be that the HP chip is actually going to be built, while the MAJC chip seems to still just be a design.

It is interesting that a number of designs lately seem to be looking to the integration of multiple CPU cores on a single chip to increase performance in server applications.

zor_prime

how about a beowolf cluster of these (0)

atif_ghaffar (464452) | more than 12 years ago | (#2461132)

sorry, could resists, there was no single grep of beowolf.

Old News (1)

Pemdas (33265) | more than 12 years ago | (#2461145)

As has been mentioned, IBM is doing this with POWER. SiByte/Broadcom has done this with an embedded processor:

EEtimes Story [eetimes.com]

Everyone in the high-performance CPU market (except itanic) is doing either this or multiple concurrent thread contexts to speed overall system computational throughput.

AMD won't be using this anytime soon... (1)

duffbeer703 (177751) | more than 12 years ago | (#2461175)

When you consider that the PA-RISC team has been transferred to that "evil" company Intel.

Re:AMD won't be using this anytime soon... (1, Informative)

Anonymous Coward | more than 12 years ago | (#2461241)

Bullshit. No we haven't. We're still right here.

"Single-transistor SRAM"? (2)

Christopher Thomas (11717) | more than 12 years ago | (#2461219)

I *thought* the cache density looked a bit high for ordinary SRAM - the article mentions something they're calling "single-transistor SRAM".

Does anyone know how on earth they're managing this? Or is this just some low-leakage variant of DRAM with added marketing spin?
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